Synchronous Dynamic Random Access Memories (SDRAMs) can provide high data bandwidth with relatively inexpensive costs. A challenge in obtaining high system performance in SDRAMs, such as Double Data Rate SDRAM (DDR-SDRAM), stems from overhead used to manage data transactions. Each transaction, such as a read or write, for example, entails a certain initial latency for setup prior to execution.
Modern microprocessor systems can be sensitive to latency in transactions involving SDRAM. Typically, microprocessors run at a much higher speed internally than a given memory subsystem. Optimized performance for the microprocessor can depend on the performance of the memory subsystem. A number of conventions are used to improve performance of the SDRAM in transactions involving a microprocessor to boost overall system performance.
One convention used to increase performance in SDRAM memory subsystems is to provide a steady data stream in a transfer mode generally referred to as a burst operation. A burst operation typically consists of a memory transaction involving a transfer of multiple data words.
Memory transactions are typically implemented using a memory controller to control the transactions between multiple components seeking to use memory resources coupled to a shared resource such as a common bus. The memory controller performs various control functions for granting access to the memory, such as arbitration between the multiple components. The memory controller typically has a control interface for receiving and sending control signals and information. A control interface can be implemented that permits the components sharing the bus to initiate random length burst operations to obtain enhanced performance. Random length burst operations are often used in PCI (peripheral component interconnect) express devices (PCIe) and DMA (direct memory access) controllers.
One known technique for dealing with control of random length burst operations in a memory processing system is to provide additional dedicated control signals. For example, control signals may be separately provided in an interface for indicating an address phase, a read or write operation phase and a final data word of a random length burst transaction. The dedicated control signal interface is shared between all the devices connected to the memory, so that an arbitration step is usually used, which adds to the overhead and latency of this approach. In addition, when being refreshed, the DRAM is inaccessible, disadvantageously resulting in additional latency using this approach.
Another known technique for implementing random length burst operations is to employ first in first out (FIFO) buffers for the data transaction. The FIFO buffers can be implemented to take advantage of pipelining techniques that can obtain high clock rates, since the data shifts, or is indexed through the FIFO buffer in a registered chain. The random length data is placed in the FIFO buffer, and then read out in a pipelined burst operation. Challenges can arise, however, in properly executing the burst operation when reading data out of the FIFO buffer in that more data may be inadvertently read than is desired for the particular data transaction. When the burst operation is executed at high speed, a logical determination of the end of the data may take longer than a transfer of a data word out of the FIFO buffer. Inadvertent reading causes data to be shifted, or indexed, out of the FIFO buffer, resulting in data loss. Furthermore, if this type of FIFO interface is implemented in a low-cost field programmable gate array (FPGA), it tends to be sensitive to timing issues, such as stopping a read operation from a FIFO buffer upon detection of the last data word.
It is possible to modify the FIFO technique, as well as the control signal interface approach, to use faster internal resources of the FPGA, such as Flip-Flop devices, but such an approach achieves limited success. For example, the use of Flip-Flop devices occupies approximately 3 times the resources in an FPGA than would be used in a conventional control signal interface. Moreover, because Flip-Flop devices are somewhat scarce in FPGA devices, it may be difficult to obtain enough resources to implement such a memory controller in an FPGA.
Another approach to solving the problem of inadvertent reading of a FIFO buffer beyond the last data word of a random length burst operation is to divide the data transaction into multiple smaller transactions. Because some types of SDRAM have a minimal transaction length of four data words (such as DDR2-SDRAM), this technique can be effective. However, for longer burst operations, a large number of small transactions are executed to achieve the data transaction. In addition, if the addresses for the data transaction are not aligned on the four word data boundary, unused write data is masked, while unused read data is discarded, leading to decreased performance issues. Moreover, two separate buffer memories are used to set up the data transaction, one buffer memory for the transaction information, and another buffer memory for payload data. If the transaction information is included in with the payload data, the performance can decrease significantly, for example, by as much as 20%.
Another technique for avoiding inadvertent reading of a FIFO buffer beyond the last data word of a random length burst operation is to mark the last data word with an identifier. However, with high-speed pipeline FIFO buffers, by the time the identifier is read and interpreted, there is not enough time to stop reading from the FIFO buffer.